Digital Electronics & Logic Design Downloads

Digital Electronics & Logic Design Course Downloads

DELD Assignment

DELD Assignment – 2 July 2024
DELD Assignment – 1 April 2024

Previous Question Papers

DE MID II QP 1 JULY 2023
DE MID II QP 2 JULY 2023
DSD EXTERNAL PAPER – FEB-MAR 2023
DSD EXTERNAL PAPER – MAR 2021
DSD EXTERNAL PAPER – DEC 2019
DE II MID QP 3
STLD II MID QP 1
STLD II MID QP 2
DE II MID QP 4
DE I MID QP 1 MAY 2023
DE I MID QP 1
DE I MID QP 2
STLD I MID QP 1
STLD I MID QP 2
STLD I MID QP 3

UNIT 1

Number Systems, Binary Codes, BCD Codes*
Solved Problems

UNIT 2

Design of Combinational Logic Circuits
Half Adder and Full Adder*
Half Subtractor and Full Subtractor*
Binary Adder-Subtractor*
BCD Adder*
Multiplexer*
Magnitude Comparator*
Code Converters*
PLDs#
PLD Notes*

UNIT 3

Sequential Circuits, Latches, Flip-Flops*
Flip-Flops

UNIT 4

Registers Introduction – Shift Registers*
Universal Shift Register – Synchronous Counters*
Asynchronous Counters*
Ring and Twisted Ring Counter*

UNIT 5

Logic Families Notes#
Logic Families
Finite State Machines

Note: * marked downloads are shared by V.Anitha

Note: # marked downloads are shared by Dr.T.Sunitha